Senior ASIC Digital Design Engineer

3 weeks ago

Ottawa, Ontario, Canada Ciena Full time

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual's passions, growth, wellbeing and belonging. We're a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute:

The Wavelogic family of products are used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. Reporting to ASIC Senior Manager, as a Senior Digital Design Engineer, in conjunction with a team of Digital and Analog Design Engineers, Verification Engineers and Architects, you'll play a key role in implementing innovative design solutions for functional blocks and subsystems for the Wavelogic family of products.

  • You will read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers, Design Primes, and architects.
  • You will be responsible for owning implementation documents, completing design capture of one or more architectural functional blocks.
  • You will be responsible for providing timing constraints for your design.
  • You will be responsible for reviewing synthesis reports and timing reports to ensure design captured meets design rules and is efficient on area and power.
  • You will participate in documentation and code reviews.
  • You will validate the sanity of your design and later supporting the verification team to ensure they achieve the desired coverage.
  • You will help with verification debug of your design and provide status updates on a regular basis.

The Must Haves:

  • Minimum Bachelor's degree in Electrical or Computer Engineering coupled with work experience in the use of System Verilog.
  • Solid and comprehensive knowledge of digital design.

Assets:

  • Experience with
    • DSP and/or Forward Error Correction
    • ASIC Digital/Analog mixed-signal
    • Using Jira for bug tracking and GIT for source code management and revision tracking
  • Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.

Pay Range:
The annual pay range for this position is $100,900 - $161,100 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

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