Design Verification Engineer

4 weeks ago

Vancouver, Canada AMD Full time

Join to apply for the Design Verification Engineer role at AMDThis range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.Base pay range$150,400.00/yr - $225,600.00/yrWHAT YOU DO AT AMD CHANGES EVERYTHINGThe CIT team is a dynamic and innovative team dedicated to pushing the boundaries of hardware development. We are seeking skilled and motivated verification engineers to join our growing team and to contribute to the success of cutting-edge IPs. We are currently looking for an experienced ASIC Design Verification engineer who will be involved in all aspects of design verification activities, using the latest methodologies with the help of automation, keeping power and performance in mind.The CIT team designs AMD chiplet technology. The Design Verification group within this team is responsible for developing a scalable DV flow with new emphasis on automation, power, and performance.The PersonWill demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail.Will have good communication and writing skills.Will have good teamwork and interpersonal skills.Key ResponsibilitiesClosely work with architects and designers to develop verification strategies and execution plans.Participate in the verification of complex IP blocks, take end to end ownership of key features for all projects.Work on test plans, test case development, testbench enhancement, regression, and coverage closure.Deploying industry-leading verification methodologies, such as UVM and Formal Verification.Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments.Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.Analyzing functional, code, and test plan coverage.Implementing assertions, checkers, and monitors.Triaging and debugging regressions.Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools.Conducting and participating in code reviews.Preferred ExperienceExtensive hardware verification experience.Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.Must have excellent programming skills.Must have exposure to Makefile and other scripting languages like Perl, Python and RubyAcademic CredentialsBachelors or Masters degree in Computer Engineering/ Electrical EngineeringLOCATION:Vancouver, BC, Markham, ONAMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. #J-18808-Ljbffr

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