ASIC Digital Design, Sr. Staff
2 days ago
Engineering
Hire Type
Employee
Job ID
6544
Remote Eligible
Yes
Date Posted
30/09/2024
Senior
Staff
ASIC
Digital
Design
Engineer
Seeking a highly motivated and innovative digital
design
engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation
NRZ and PAM-based SerDes
products.
Strong theoretical and practical background in high-speed serializer and data recovery circuits is a strong plus. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.
The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have
an initial
training done by the top experts in the field as well as continuous
on the job
training and assignments. The work is
very challenging
, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.
Key Qualifications BSEE or
MSEE plus a minimum of
8
years of digital design and verification experience in the industry Good experience
in writing block-level test-cases including constrained directed random tests Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is
required Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows Scripting experience in Shell, Perl, Python and TCL is a plus Good theoretical and practical understanding of digital signal processing and data recovery circuits is
required Good communication
skills for interacting between
different design
groups and customer support teams are
required Must be self-motivated, proactive, and able to balance
good design
quality while meeting tight deadlines Resolves issues in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutions May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise Must
exhibit
ability to produce
good results
as an individual and team contributor
Preferred Experience RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools Enhancing and
maintaining
existing SERDES PHY IPs supporting multiple protocols Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
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Ahuntsic North, Canada Synopsys Full timeCategory Engineering Hire Type Employee Job ID 6544 Remote Eligible Yes Date Posted 30/09/2024 Senior Staff ASIC Digital Design Engineer Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal...
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