Staff Engineer, Digital Design

3 weeks ago


Ottawa, Canada Synopsys Full time
ASIC or FPGA Digital Design, Staff or Sr.Staff Engineer

Key Qualifications

  1. BSEE or MSEE with relevant digital design experience in the industry.
  2. Must be familiar with Verilog and VCS.
  3. Good knowledge of back-end synthesis tools DC/PT is desirable.
  4. Scripting experience in Shell, Perl, Python, and TCL is a plus.
  5. Good theoretical and practical knowledge of digital signal processing and data recovery circuits is desirable.
  6. Good communication skills for interacting between different design groups and customer support teams are required.
  7. Must be self-motivated, proactive, and able to apply good design quality while meeting tight deadlines.
  8. Resolves issues in inventive ways and exercises sound judgment in selecting methods and techniques to obtain solutions.

Preferred Experience

  1. RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog.
  2. Strong experience of ASIC Digital Design, front end experience.
  3. Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
  4. Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
  5. Enhancing and maintaining existing SERDES PHY IP.
  6. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams.
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