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Senior Staff Digital Design Engineer
1 month ago
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:We are seeking a highly motivated and innovative digital design engineer with a strong background in ASIC development flow. You are passionate about technology and eager to work on the cutting edge of digital and mixed-signal designs. You have a firm grasp of high-speed serializer and data recovery circuits, and are excited by the opportunity to work on the next generation of NRZ and PAM-based SerDes products. You thrive in dynamic environments and are always looking for new challenges. You are a team player who communicates effectively with different design groups and customer support teams. You exhibit a proactive and self-motivated attitude, balancing good design quality while meeting tight deadlines. You are creative in resolving issues and exercise independent judgment in selecting methods and techniques to obtain solutions. You are capable of producing excellent results both as an individual contributor and as part of a team.
What You’ll Be Doing:- Developing and verifying digital designs for high-speed serializer and data recovery circuits.
- Writing block-level test cases, including constrained directed random tests.
- Interacting with different design groups and customer support teams to resolve technical issues.
- Defining synthesis design constraints and resolving STA issues.
- Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols.
- Performing functional and performance tests on prototype test-chips.
- Contribute to the development of high-speed serializer and data recovery circuits, pushing the boundaries of technology.
- Help accelerate the integration of more capabilities into an SoC, meeting unique performance, power, and size requirements.
- Enable the creation of differentiated products that get to market quickly with reduced risk.
- Support the continuous innovation of our Silicon IP portfolio.
- Collaborate with expert teams to deliver high-end mixed-signal designs.
- Ensure the highest quality of digital design and verification processes.
- BSEE or MSEE
- Experience in writing block-level test cases, including constrained directed random tests.
- Proficiency in Verilog and VCS, and knowledge of back-end synthesis tools DC/PT.
- Understanding of digital design methodologies, ATE production testing, DFT insertion, synthesis constraints, and flows.
- Scripting experience in Shell, Perl, Python, and TCL is a plus.
- Self-motivated and proactive with the ability to meet tight deadlines.
- Strong communication skills for effective interaction with different design groups and customer support teams.
- Creative in resolving issues and exercising independent judgment in selecting methods and techniques.
- Capable of guiding junior peers and networking with senior personnel.
- A team player who can produce good results both individually and collaboratively.
You will be part of a highly experienced mixed-signal design and verification team. This team is responsible for developing the next generation of NRZ and PAM-based SerDes products. You will collaborate with expert digital and mixed-signal engineers, working on high-end mixed-signal designs from specification development to functional and performance testing on prototype test-chips. The team is dynamic and constantly facing new challenges due to technological changes and the need for innovation.
Rewards and Benefits:We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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