Design Verification Director

3 weeks ago

Markham, Canada Huntech USA LLC Full time

Bring your proven ASIC Verification leadership experience to build and lead a team that will contribute to the functional verification of designs from coming up with block level and system level verification plan to writing test sequences, test execution, collecting and closing coverage. Our SoC customer is growing rapidly in their nascent Markham Design Centre, offer interesting and varied silicon connectivity solutions to remove data bottlenecks and enable large AI workloads to flow seamlessly for their major customers including all the major GPU vendors, hyperscalers, CSPs in the Data Center ecosystem

Basic qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required and Masters degree preferred.
≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
Knowledge of industry-standard simulators, revision control systems, and regression systems
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind

Required Experience
Experience with interpreting PCIe/CXL standard protocol specifications to come up with verification plan and execute them in simulation environments.
Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties and analyzing coverage data.
Must have prior experience using Verification IPs from 3rd party vendors for PCIe/CXL (with focus on Gen3 or above)
Develop VIP abstraction layers for sequences to simplify and scale verification deployments.
Currently based locally or open to relocation.

Preferred Experience
Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe /CXL protocol
Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
Experience in analyzing performance metrics of CXL/PCIe
Experience in system level verification for PCIe/CXL

We are also looking for a Principal and Team Lead, Design Verification, Digital (IC) Design Engineering Director ideally with SerDes experience and a Principal Firmware Engineer with PCIe experience.

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