Verification Engineer
1 week ago
JOB RESPONSIBILITIES:
- Work with RTL designers, system architects, and block level verification engineers to develop top-level verification requirements and test plans based on specifications.
- Develop, maintain, and publish verification specifications.
- Analyze and debug simulation failures.
- Generate code coverage and functional coverage report.
- Participate in the development of department level processes, including the documentation of processes and procedures, and recommendations for improvements to existing processes.
- Create, track, and close bugs in bug tracking tool.
- Gate level simulations.
- Regression analysis.
REQUIRED SKILLS:
- Fluent in UVM and System Verilog.
- An understanding of object-oriented concepts and experience designing class-based test benches.
- Experience in writing test plans and creating directed and random test cases.
- Strong scripting skills in Perl, Python, shell, etc.
- Strong problem-solving skills to quickly identify and provide a solution under tight schedule pressure.
- Excellent written and oral communication skills.
- ASIC design experience considered an advantage.
- Experience of mathematical modeling in MATLAB, Python, or similar considered an advantage.
- Experience of wired/wireless protocols considered an advantage.
- Experience working with FPGA-based prototyping considered an advantage.
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