Senior ASIC Verification Engineer – SystemVerilog

3 days ago

Ottawa, ON, Canada Synopsys Inc Full-time $90,000 - $140,000 Contract

Synopsys Inc in Ottawa is seeking an experienced ASIC Digital Verification Engineer with a strong background in SystemVerilog and UVM to verify complex ASIC designs, including next-gen HBM products.

You will develop verification plans, debug testbenches, automate flows with Python or Perl, and contribute to design reviews. Join a collaborative team delivering high‑quality silicon and advancing verification methodologies.