Senior ASIC Design Verification Technical Lead

Scaledge Technology Ltd. is seeking a

Senior ASIC Design Verification Technical Lead

to provide technical leadership for ASIC, SoC and subsystem verification projects.

The successful candidate will lead verification activities, coordinate technical tasks within verification teams, develop verification environments and test strategies, and work closely with design and cross-functional engineering teams to achieve verification and coverage objectives.

The position requires strong hands-on experience in

SystemVerilog, UVM, RTL verification, subsystem verification and simulation/debugging , together with experience leading verification teams.

Key Responsibilities Company:

Scaledge Technology Ltd.

Job Type:

Permanent, Full-Time

Location:

British Columbia, Canada

Work Arrangement:

On-site

About the Position Scaledge Technology Ltd. is seeking a

Senior ASIC Design Verification Technical Lead

to provide technical leadership for ASIC, SoC and subsystem verification projects.

The successful candidate will lead verification activities, coordinate technical tasks within verification teams, develop verification environments and test strategies, and work closely with design and cross-functional engineering teams to achieve verification and coverage objectives.

The position requires strong hands-on experience in

SystemVerilog, UVM, RTL verification, subsystem verification and simulation/debugging , together with experience leading verification teams.

Key Responsibilities

Lead and coordinate ASIC, SoC and subsystem design verification activities.

Provide technical guidance to verification engineers and coordinate day-to-day verification tasks.

Plan and execute verification activities according to project requirements and milestones.

Develop verification plans, test plans and targeted test cases for ASIC and subsystem designs.

Design, develop and maintain

UVM-based verification environments .

Integrate and configure verification IP and interface components within verification environments.

Develop and maintain Register Abstraction Layer (RAL) models and related register verification tests.

Develop constrained-random and directed test cases to verify functional requirements and identify design corner cases.

Execute simulations and analyze regression results to identify failures and potential RTL/design issues.

Debug RTL and verification failures using simulation and waveform-analysis tools.

Develop and monitor functional and code coverage and coordinate activities required to close coverage gaps.

Develop performance-monitoring and performance-verification test cases where required.

Support verification of Ethernet and other high-speed communication interfaces and subsystems.

Participate in formal verification activities, including assertion-based verification and property checking, where applicable.

Coordinate with RTL designers, architects and other engineering teams to investigate and resolve technical issues.

Track verification progress, technical issues, test execution and coverage status.

Prepare technical documentation and communicate verification status and issues to project stakeholders.

Mentor and provide technical guidance to junior verification engineers.

Contribute to improvements in verification methodologies, reusable environments and project execution processes.

Required Qualifications

Bachelor's degree in

Electrical Engineering, Electronics Engineering, Computer Engineering, or a related engineering discipline .

7+ years of professional experience

in ASIC, SoC, subsystem or semiconductor design verification.

Experience providing

technical leadership or coordination of ASIC/design verification teams .

Strong hands-on experience with

SystemVerilog and UVM .

Experience developing and maintaining UVM-based verification environments.

Experience developing verification plans, test cases and verification strategies.

Experience with

RTL debugging, simulation, regression execution and issue resolution .

Experience with functional and code coverage analysis and verification closure.

Experience with one or more hardware/interface protocols such as

Ethernet, AXI, APB, UALink, MACsec or comparable protocols .

Experience with verification tools such as

Synopsys VCS, Verdi, QuestaSim, ModelSim, Cadence JasperGold or equivalent tools .

Ability to coordinate technical activities and provide guidance to other verification engineers.

Strong analytical, problem-solving and communication skills.