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Senior Digital Verification Engineer
2 months ago
Job Summary
TSMC is seeking a highly skilled Digital Verification Engineer to join our team in Ottawa, Canada. As a key member of our Verification team, you will be responsible for designing and implementing digital verification methodologies and tools to ensure the quality and reliability of our semiconductor products.
Key Responsibilities
- Design and implement digital verification methodologies and tools to ensure the quality and reliability of our semiconductor products.
- Develop and maintain complex digital verification environments, including testbenches and simulation scripts.
- Collaborate with cross-functional teams, including design, verification, and manufacturing, to ensure seamless integration of digital verification methodologies.
- Develop and maintain expertise in digital verification tools and technologies, including Verilog, SystemVerilog, and UVM.
- Contribute to the development of verification planning, code and functional coverage, assertion-based verification, and formal verification methodologies.
- Work with design teams to validate digital circuit implementations, develop testbenches, perform functional verification, and debug failing tests.
- Contribute to the customization of standard digital verification methodologies and help improve the electronic design automation (EDA) capabilities of the group.
Requirements
- Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
- 8+ years' experience in digital design verification and Verilog testbench and Universal Verification Module (UVM) development.
- Logic and timing simulation using Verilog simulation tools (VCS, NCVerilog).
- Experienced in large scale chip design and sign-off process.
- Knowledge of Nano scale technology issues and challenges.
- Ability to communicate effectively (verbal and writing) in English.
Preferred Qualifications
- Experience in circuit level verification using SPICE simulation tools.
- Demonstrated ability to work well with teams in diverse locations and time zones.
- Experience with Design for Test Techniques, implementation, and verification.
- Strong problem-solving and analytical skills.
- Experience writing and debugging simulation testbenches and tools, as well as proficiency in SystemVerilog, Universal Verification Module (UVM), assertions, system level verification methodologies and debugging tools.
- Experience with verification planning, code and functional coverage, assertion-based verification, and formal verification is a definite plus.
- Working knowledge of Unix/Linux operating systems, scripting languages, and EDA tools such as Synopsys VCS or Cadence Incisive tools.
About TSMC
TSMC is the world's first and largest semiconductor foundry, established in 1987. We offer the world's most advanced process technologies and employ over 70,000 people worldwide. Our Design Technology Canada (TDTC) team is focused on the research and design of deep sub-micron circuits to better serve and support the manufacturing needs of our foundry customers and 3rd party vendors.
TSMC is committed to employing a diverse workforce and provides equal employment opportunities for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, genetic information, or any other characteristic protected by the Employment Equity Act and other application legislation in Canada.
