Senior Design Verification Engineer

1 week ago


Vancouver British Columbia, British Columbia, Canada Wipro Full time

Title: Design Verification Engineer

Duration: Full Time

Location: ​Vancouver, Canada

Description :

  • Knowledge of System Verilog and recent verification methodologies (UVM)
  • System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects
  • Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests
  • Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components
  • Ethernet Packet Processors, buffer managers, DMA engines etc
  • PHY layer verification of serial interfaces such as Ethernet, PCIe, USB etc.
  • Solid Linux environment skills including the use of Perl, Python or TCL to write/debug CAD tool scripts.
  • Experience participating in the full life cycle of ASIC projects (architecture through silicon to production)
  • Experience setting up and debugging gate level simulations with SDF annotated timing.


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