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Design Verification, Principal Engineer

3 months ago

Canada, CA Marvell Technology Full time
Design Verification, Principal Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Compute and Custom Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.

What You Can Expect

  • In this role you will be working on the verification of highly complex SoCs as well as multi SoC systems

  • Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.

  • Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete.

  • Develop tests and tune the environment to achieve coverage goals.

  • Debug failures and work with designers to resolve issues.

  • Architecting, developing, and maintaining tools to streamline the design of state-of-the-art multicore SoCs.

  • Experience with analysis/closure of code and functional coverage

What We're Looking For

Bachelor’s degree in Electrical Engineering or related fields and 10+ years of related professional experience.
Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience.

  • Proficient in System Verilog and Object-oriented programming

  • Well versed with UVM/VMM methodology

  • Knowledge and experience in Memory Interface Subsystem (DDR, LPDDR, HBM) and in complex multi chip verification environment a big plus.

  • Hands-on knowledge of ARM/RISCV processor-based subsystem verification.

  • Has worked on complex chips such as CPUs, GPUs, NOCs, Switches, Machine Learning chips etc. owning full chip, subsystem and block level verification or significant TB development including agents, drivers, checkers, interfaces etc. for a complex design

  • Has seen full verification cycle from Architecture to Tapeout with good understanding of Testplan development, debug, coverage closure and Gate sims.

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