Senior Product Verification Engineer
1 week ago
Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.
We push the limits of innovation to solve the world's most important challenges. This includes verifying PCI Express/CXL design using latest UVM standard and develop comprehensive test plan to ensure coverage closure. Candidate will also apply low power verification methodology and measure overall system performance of our IP. The position allows exposure to all aspect of ASIC design stages.A successful candidate will work with senior silicon design engineers. Develop new models in UVM or system C++
Using industrial scripting languages to automate the current working flows
Execute a project independently with global teams to achieve pre-defined goals in time
Understand logical design architecture and provide the analyzed data to architects for review
Build up UVM test bench with advanced design verification methodology
Bring up new design features
Accountable for project delivery.
Considered technical leader across project and departmental boundaries and has a proven track record for sustained innovation.
Responsible for projects or processes of significant strategic or commercial importance for project/program results
Makes technical decisions that have a significant impact on product families, go to market strategies and customer satisfaction
Elevating current ASIC design verification quality and the simulation efficiency to higher level
Rich experience in constructing highly scalability, configurability and reusability DV test bench.
Strong experience in ASIC design/verification related field in IP, Subsystem or SOC level
Writing experience in System Verilog and/or System C models for simulation
Writing UVM models, checkers and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
Compose test plan and validation vectors to ensure functional completeness
Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
Be versatile in any one of the high level verification flow such as SV,UVM, C++ etc
ACADEMIC CREDENTIALS:
~ Bachelors orMastersdegree in computer engineering/Electrical Engineering
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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