RTL ASIC Design Engineer
2 weeks ago
Vancouver, British Columbia, Canada
Permanent
Job Description:
- 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.
- Expertise in Verilog & System Verilog is a must.
- Experience in Synthesis / Understanding of timing concepts for ASIC is required.
- Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
- Hands on experience in Multi Clock designs, Asynchronous interface is a must.
- Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.
- Knowledge of low power concepts and experience is a plus.
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RTL ASIC Design Engineer
2 weeks ago
Vancouver, British Columbia, Canada Wipro Full timeRTL ASIC Design Engineer in Vancouver, British Columbia, CanadaJob Description: Minimum of 8 years of experience with Logic design, micro-architecture, and RTL coding. Proficiency in Verilog and System Verilog is essential. Previous exposure to Synthesis and deep understanding of timing concepts for ASIC is necessary.
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ASIC/RTL Engineer/Lead
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