Design Analysis Engineer
4 days ago
Design/implement various state-of-the-art, DDR PHYs (DDR5)
• Develop RTL and work closely with multiple cross functional teams, to successfully close the design – example : Work on designs to close timing, lint clean and CDC, work with verification team on planning tests for a feature, adding system verilog assertions to design constraints, participating in code reviews, presenting in waveform reviews.
Solid knowledge in fundamental digital design techniques, background in DDR5 PHY is a must.
• Verilog coding skills, System verilog coding and basic C skills are highly desired.
• Tools such VCS, Spyglass, Verdi, Unix, Perforce, Python, PrimeTime.
• Experience with Unix/Linux environments
LanceSoft is rated as one of the largest staffing firms in the US by SIA. We are driven to use the power of our global network to connect businesses with the right people, and people with the right businesses without bias. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.
This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. Click here to visit our website -
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Piping Analysis Engineer
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Piping Analysis Engineer
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System-on-Chip Design Engineer
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Product Design Systems Engineer
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Reliability Engineer
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SoC Design Engineer
4 days ago
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Reliability Engineer
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Reliability Engineer
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