Validation Engineer/Senior Validation Engineer

4 weeks ago

Ottawa ON, Canada USA Tech Recruitment Full time

UVM Verification Engineer - SystemVerilog / Verilog / OVM Are you a senior Verification Engineer with 10+ years' industry experience?Want to join a world semiconductor company focused on ASIC and FPGA design and verification, and embedded software in Canada?They are looking for a number of UVM Verification Engineers to join the team in Canada on a permanent basis.They can offer fully remote work from inside Canada and can even support relocation to Canada so international applicants are encouraged.Please note - remote work from outside Canada is not availableSound good?Develop verification environment architecture using UVMDocument test environment associations and write test casesEmploy constrained random verification approaches when possibleSupport lab bring-up with direct test casesPerform code and functional coverageWhat we look for in return is:10+ years of experience in ASIC verification.Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.Familiarity with constrained random verification techniques, assertions and functional coverage.Experience with SONET, OTN, Ethernet, PCIe is a significant asset.comBy applying to this role you understand that we may collect your personal data and store and process it on our systems.

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