ASIC Verification
3 weeks ago
Role: ASIC Verification Engg
We are looking for enthusiastic individuals with strong problem-solving abilities, excellent communication and a desire to learn. Technically, a solid foundation of digital design (VHDL, Verilog) and object-oriented programming is desired.
Minimum Qualifications for senior positions:
All minimum qualifications listed for junior positions
Minimum of 12 years of experience in ASIC/SoC design and/or verification environment
Very strong debugging and problem-solving skills supported by relevant experience
Digital logic design and implementation in advanced technology nodes
Working experience in UVM environment
Languages: C, C++, Python, Java, Verilog (or VHDL), SystemVerilog
Preferred Qualifications for senior positions:
Leadership skills
Familiarity with formal verification methods
Familiarity with standard ASIC/SoC design flows including synthesis, DFT, STA, UPF, and ECO flows
Experience in low-power design techniques
Working knowledge of NVMe, PCIe, DDR and ARM standards
Familiarity with big box emulation platforms
Proven ability to architect and lead IP/SoC-level verification efforts
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