Physical Design Engineer

Join to apply for the Physical Design Engineer role at AMD This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $103,200.00/yr - $154,800.00/yr WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role We are seeking an adaptive, self‑motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high‑performance, power‑efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full‑chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs. The Person You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full‑chip floorplanning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem‑solving abilities, are eager to learn, and thrive in tackling complex design challenges. Key Responsibilities Extensive hands‑on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus Solid understanding of low‑power design methodologies, including power‑aware synthesis and place‑and‑route; familiarity with voltage domain checks is advantageous Proven experience in chip‑level floorplanning, including feedthrough topology planning, repeater insertion, and top‑level port/pin assignment Tapeout experience across multiple projects Preferred Experience Proficiency in EDA tools such as Design Compiler (DC) and Innovus/ICC2 Skilled in Static Timing Analysis (STA) tools and techniques Strong grasp of floorplanning and layout techniques compliant with foundry design rules Experience with scripting languages including TCL, Perl, and Python Excellent communication skills—written, verbal, and listening Strong interpersonal skills; adaptable, collaborative, and a dedicated team player Academic Credentials Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering LOCATION: Markham, ON Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr