Senior ASIC Verification Engineer with Expertise in SystemVerilog and UVM
6 days ago
A prestigious Semiconductor design company is seeking an experienced ASIC Verification Engineer to join their team, working on cutting-edge projects across various products in the Semiconductor space.
About the RoleThis Senior ASIC Verification Engineer position involves contributing to the success of prime ASIC projects at advanced technology nodes, reaching down to 3nm FinFET. The successful candidate will leverage expertise in SystemVerilog, UVM, and scripting languages to drive verification activities and employ state-of-the-art methodologies and tools to validate designs.
The key responsibilities include:
- Verification activities for assigned blocks or entire chips, ensuring strict adherence to project timelines.
- Developing robust verification environments utilizing expertise in SystemVerilog, UVM, and scripting languages.
- Documenting test environment associations and creating comprehensive test cases to validate design functionality.
- Applying constrained random verification approaches to enhance test coverage.
- Providing direct support for lab bring-up, executing test cases, and troubleshooting as needed.
To be successful in this role, the ideal candidate should possess:
- Eight or more years of experience in ASIC verification with a proven track record of delivering successful projects.
- Proficiency in Verilog, SystemVerilog, and other hardware description languages.
- Expertise in scripting languages.
- Extensive experience with OVM/UVM methodologies, showcasing a deep understanding of advanced verification techniques.
- Familiarity with constrained random verification techniques, assertions, and functional coverage.
The estimated salary for this position is approximately €120,000 - €180,000 per annum, depending on experience and qualifications.
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