Senior Engineer II

Senior Engineer II - Validation at Microchip Technology Inc. Microchip’s Data Center Solutions (DCS) Business Unit delivers industry‑leading performance, reliability, and security through storage controllers, memory controllers, NVMe SSD controllers, PCIe switches, and SAS expanders. Job Description As a System Validation Engineer, you will help bring‑up, integrate, and validate advanced System‑on‑Chip (SoC) products for the DCS Business Unit. The role involves building prototype ecosystems, developing test infrastructure, and executing pre‑ and post‑silicon tests to ensure SoC functionality meets design specifications and industry standards. Responsibilities Integrate prototype SoC device hardware and firmware into complete solutions, bringing system‑level solutions to life and enabling functional testing and firmware development. Develop, execute, and document feature‑tests that validate SoC operation, ensuring components and overall SoC meet performance and industry requirements. Work with pre‑silicon FPGA emulation platforms and post‑silicon prototype ICs/SOCs. Build and maintain test infrastructure, including boards, FPGAs, embedded software, device drivers, and test bench scripts. Develop block, subsystem, and system‑level test firmware and scripts, integrating them into best‑in‑class automation suites. Lead activities in technical areas and supervise junior engineers. Run complex tests and conduct investigations in lab environments on‑site and remotely. Integrate AI‑based tools to optimize daily testing routines. Identify, report, and investigate bugs, collaborating with cross‑expertise teams. Apply knowledge of devices, systems, protocols, and industry standards dynamically. Help grow and train the validation team. Present technical information to internal and external groups effectively. Requirements / Qualifications Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. 5+ years of relevant industry experience. Prior experience in IC and SoC validation. Hands‑on experience with prototype ICs, boards, and hardware infrastructure. Proficient in lab environments; familiar with test equipment and protocol analyzers. Skilled in SoC debug and investigation using firmware and MIPS debug environments. Strong understanding of digital systems and computer architecture. Solid foundation in Data Communication and Digital Design theory. Proficient in scripting languages (Python, Tcl/Tk) and C/C++ programming. Demonstrated analytical and problem‑solving abilities. Experience defining comprehensive test coverage at sub‑block and system levels. Ability to develop and execute functional validation test plans and validation software/scripts with minimal supervision. Knowledge of PCIe system architecture and protocol; ability to read and analyze PCIe protocol traces. Familiarity with SAS/SATA, PCIe, DDR, I2C, SPI protocols (asset). Thorough knowledge of circuit theory and high‑speed signal fundamentals. Quick learner of new technologies, protocols, and standards. Effective team player; collaborates well with peers and cross‑functional groups. Strong communication and interpersonal skills. Other Useful Qualifications SoC performance validation and tuning experience (asset). Experience with prototype boards, board modifications, and schematic reading. Hands‑on hardware experience with x86‑based systems. Experience in Linux and Windows OS environments. Familiarity with AI‑based tools and their integration into workflow. Experience with PCIe and CXL compliance testing (asset). Testing and debugging high‑speed SERDES. Familiarity with FPGA‑based emulation environments and pre‑silicon test coverage deployment (asset). Experience in high‑speed digital design, board design, PCB layout, signal integrity, and manufacturing processes (asset). Experience developing and debugging MIPS‑based architectures; firmware programming in C/C++. Working knowledge of protocols: PCIe, CXL, DDR, NVMe, ONFI, SAS, SATA, I2C, SPI; protocol trace debugging. In‑depth knowledge of Linux OS architecture and drivers. Linux or Windows host driver development experience. Knowledge of FPGA layout tools and VHDL/Verilog coding. ThreadX or RTOS knowledge. Travel 0% – 25% travel required. Compensation Annual base salary range: $86,000 – $186,000.* #J-18808-Ljbffr