Design Technology Co-Optimization Layout Analysis Engineer

4 weeks ago


Toronto, Canada Intel Corporation Full time

Design Technology Co-Optimization Layout Analysis EngineerWe are seeking a Design Technology Co-Optimization Layout Analysis Engineer to join our DTCO team. This role focuses on analyzing and optimizing circuit performance through advanced modeling, simulation, and cross-functional collaboration between design and technology teams. The successful candidate will drive circuit-level analysis to enable optimal technology node development and design methodology improvements.ResponsibilitiesPerform detailed circuit analysis using industry-standard simulation tools (SPICE, Spectre, etc.).Develop and maintain circuit models for various technology nodes and process variations.Analyze circuit performance metrics including timing, power, area, and reliability.Create and validate compact models for emerging device technologies.Collaborate with process technology teams to optimize device characteristics for circuit performance.Work with design teams to understand circuit requirements and translate them into technology specifications.Perform trade-off analysis between different technology options and design approaches.Support technology roadmap planning through circuit-level performance projections.Develop and improve circuit analysis methodologies and flows.Create automated analysis scripts and tools to enhance productivity.Establish best practices for circuit characterization and optimization.Support the development of design rules and guidelines.Partner with Technology Development, Design Engineering, and CAD teams.Present analysis results and recommendations to technical and management teams.Support customer engagements and foundry service activities.Participate in design reviews and technology milestone assessments.Strong analytical and problem-solving abilities.Excellent communication skills.Ability to work effectively in cross-functional teams.Detail-oriented with strong organizational skills.Self-motivated with ability to manage multiple projects simultaneously.QualificationsBachelor’s degree in Electrical Engineering, Computer Engineering, or STEM related field and 3+ years of experience.Experience in analog layout design.Designing and analyzing local layout effects in advanced nodes (5nm and lower).Evaluating and reducing parasitic impact on performance critical circuits.Experience with emerging device technologies (FinFET, GAA, etc.).Post graduate degree (preferred).Experience with process monitoring circuits (preferred).Experience with machine learning applications in circuit optimization (preferred).Experience with EDA tool development and customization (preferred).Experience in foundry or fabless semiconductor environment (preferred).Publications in relevant technical conferences or journals (preferred).EEO StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr



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